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Cavium's XPliant Ethernet chip sets new standard for programmability

Cavium claims its programmable XPliant Ethernet chip can support new protocols via software updates without adding latency to the data plane.

Semiconductor manufacturer Cavium announced a new family of programmable Ethernet switch chips it claims will allow switch manufacturers to dramatically decrease -- from years to months -- the time it now takes them to add new protocols and features to their devices.

Unlike merchant silicon from leading network chip makers such as Broadcom and Intel, Cavium's XPliant family of chips, the fruits of a July acquisition of XPliant Inc., are not hard-coded. Cavium can add new protocols and features to the chips through software updates. Switch manufacturers will have that option, too.

"XPliant gives vendors the ability to build differentiated products," said Dan Tuchler, marketing executive with Cavium's XPliant business. "If you have switches powered by the same [hard-coded] silicon as everyone else, your feature set is the same as everyone else's. We're able to give them a platform where they can add their own features and innovation in the chip, innovations that suit their target market very well. Maybe it's a new kind of monitoring, a new private protocol for acceleration. They have the tools to do that."

Cavium will offer four chips in the XPliant family, with varying amounts of throughput to match different use cases. Total throughput will range from 880 Gbps to 3.2 Tbps. A mid-range model that runs at 1.28 Tbps is comparable with leading switch chips from Broadcom and Intel. The top-end XPliant CNX88091, with 3.2 Tbps of throughput, is more than twice the throughput of the leading chips on the market today. It will support 128x25 Gbps switching lanes, allowing for switches with 32x100 Gigabit Ethernet ports, 64 ports of 50 or 40 GbE, or 128 ports of 25 or 10 GbE.

While the XPliant chips' speeds and feeds advantage will be short-lived as Broadcom and others catch up, the programmability of these chips will be hard for competitors to match, said Joe Skorupa, vice president and distinguished analyst at Gartner.

Cavium won't have to build a new chip every time the IETF or IEEE approves a network protocol. The two- to three-year cycle of adding new features and protocols to an Ethernet switch chip will be shortened to the two months it takes to write and validate the software into an existing chip.

This accelerated innovation is becoming extremely important in networking, said Bob Wheeler, principal analyst with The Linley Group.

"Every time one of these new protocols is introduced to fixed-function switches, you have to do a spin of the silicon to add support for the protocol," he said. "What's happened, particularly because of virtual switches implemented in hypervisors, those protocols are evolving at the pace of software instead of silicon."

As an example of the silicon's programmability, the XPliant chips will support the network virtualization protocol Generic Network Virtualization Encapsulation (GENEVE) immediately upon release. GENEVE was submitted to the IETF this spring by VMware, Microsoft and Red Hat as an enhanced alternative to VXLAN and NVGRE, the encapsulation protocols that VMware and Microsoft use in their respective network virtualization software. Typically, a chip designer would need two or three years to bring an Ethernet chip to market that supports such a new protocol.

That said, few people are going to care about GENEVE support today because none of the network virtualization vendors are ready to implement it in their software yet, Skorupa said. "The more important issue is, depending on the application, you can build the right feature set for it [in your switch]," he said. "Being able to put a software load into a switch optimized for a particular use case could be very interesting."

XPliant's chips will give switch manufacturers and network operators the ability to change the very nature of a switch through a simple software change, Skorupa said. For instance, in a leaf-and-spine network, a network architect will place switches with large MAC tables in the leaf layer and switches with large IP tables in the spine layer. Typically, a network operator would buy switches with differentiated silicon for each layer of the network. XPliant's programmability would allow the same switch to serve in either layer of such a design. A vendor's software would determine the size of MAC and IP tables in the switch, rather than the micro-code of the chip designer.

This approach also simplifies how network engineers handle the stocking of spare switches. If a switch fails, network engineers can rack and wire a generic spare and load up a software image appropriate to whichever network layer the engineer places it in.

If a new version of an SDN protocol hit the market -- OpenFlow 2.0, for instance -- that same IT organization's switch vendor could add support for the protocol through a software update. Then the networking team could change its Layer 2/3 network to OpenFlow 2.0.

Furthermore, switch vendors will be able to create new protocols to address the needs of specific customers. If financial service companies want a protocol that helps them prove compliance with regulatory controls, a switch vendor could build the protocol and install it on switches via a software update. Normally, a vendor would have to ask a chip maker to design new silicon to support that protocol.

"I think there is really interesting potential here," Skorupa said. "If [Cavium delivers], that's a real breakthrough."

In the past, network equipment vendors have added programmability by embedding network processors or FPGA chips into their products. However, these hybrid approaches add latency to the data plane, Skorupa said.

Cavium declined to reveal how it achieved this level of programmability, citing the patent-pending nature of XPliant. However, Tuchler said the programmable data plane of the XPliant chips adds no latency to the system.

XPliant's ability to maintain consistent latency on a programmable data plane will mean very little if the baseline latency of the chip was already high, Skorupa said.

Cavium isn't ready to specify latency figures for the chips, nor the price the company will charge for them, but Tuchler said both will be "comparable" to leading switches on today's market.

The XPliant chips are probably a year away from shipping in large numbers. Cavium will start sending samples and evaluation boards to switch manufacturers by the end of this year. A software development kit with APIs and a full baseline feature set of Layer 2/3 and SDN protocols is available now. Cavium is also offering a "White Model" simulator in its own labs where switch designers can test their software.

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If your vendor could write custom protocols into the data plane, what would you ask for?
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A Key feature to innovate in switches is the capability to modify address Learning, blocking the Learning of an address for some time at all switch port after address is Associated to th First Port that receives the frame.see arp path protocol, first-arrival Port and others that propose flooding of broadcast through all links to find shortest path, instead of Computing the route with ljnk state protocols.
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More precisely, blocking the relearning of an address at other ports than the First arrival Port.

another feature would be Learning only addresses from some types of frames, like ARP Request or Reply.

Another one would be to learn both source and destination ddresses, transport ports...

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