In today's data center there are two major problems -- space and power consumption. But networking vendors -- namely Cisco -- are not doing enough to make change. These vendors must rethink chip design and packaging in order to slash network power consumption.
- Cisco products, for example, consume extraordinary amounts of power when compared to, say, Intel CPUs or other data center infrastructure elements. At NANOG 54, Cisco technical marketing engineer Lawrence J. Wobker presented a session called "Power Consumption in High-End Routing Systems" in which he made the following claims "explaining" extreme network power consumption:
- Router port density is increasing and this drives more power consumption.
- As silicon processors get larger, they use more power and need more fans, thus creating a non-linear power consumption model.
- Fan power consumption is variable -- hotter data centers use more power for fans.
- Power supplies consume only 10% of power; meanwhile; linecards consume 70% of total power.
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These points are valid and probably correct, at least when it comes to Cisco's strategy of cramming more and more services, features and functions into platforms. But any engineer who has seen the C6500 Supervisor module can attest to the sheer number of chips and their physical size.
An Intel server has just a few chips while Cisco uses dozens of custom ASICs. One wonders if this is necessary. Intel is improving power efficiency -- the last generation of Intel CPUs have reduced power consumption from around 150 W per CPU (Paxville) to approximately 95 W on the Core 2 Xeon (Conroe), and today around 80 W for Core 2 Xeon (Clovertown) units. Almost 50% reduction in the last five years is a good effort.
Intel has achieved these power reductions by focusing on power-efficient chip designs and primarily reducing the silicon production die from 90 nm to today's 22 nm sizing. As the die process gets smaller, less power is consumed. In addition, Intel has drastically reduced the number of chips by aggregating functions into a single die. Case in point, the latest Intel CPUs include the memory interfaces in the main CPU die instead of the Northbridge chipset.
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Yet, Cisco, and most other network silicon vendors, aren't delivering smaller dies. They still use older and cheaper fabrication at 120 nm and 90 nm. Cisco continues to assert that it will develop and manufacture its own silicon as a key part of its innovation strategy. We should demand that power reduction be a key part of this innovation. Cisco should be capable of using modern chip die packaging and updating its designs to use low power design techniques.
Some network vendors are already making progress. While the Cisco Nexus 7010 typically needs around 8 kW, the Arista Networks 7100 chassis consumes a maximum of 3.8 kW with fully loaded chassis and all ports at 100%. An even newer switch, the Gnodal GS0072, can deliver 72 x 40 gigabit Ethernet ports and draw less than 1.8 kW because of its latest generation chip packaging choices and efficient chip design.
It's not enough to offer better power supplies and more efficient fans. The real power consumption is in the silicon, and that requires commitment to new skills in the chip design process.
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Greg Ferro, Contributor asks:
How do you think Cisco could improve its chip design?
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